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lp621024d-t series 128k x 8 bit cmos sram (july, 2005, version 1.2) amic technology, corp. document title 128k x 8 bit cmos sram revision history rev. no. history issue date remark 1.1 add pb-free package type august 19, 2004 final 1.2 remove non-pb-free package type july 3, 2006
lp621024d-t series 128k x 8 bit cmos sram (july, 2005, version 1.2) 1 amic technology, corp. features general description ? single +5v power supply ? access times: 55/70 ns (max.) ? current: very low power version: operating: 70ma (max.) standby: 50 a (max.) ? full static operation, no cl ock or refreshing required ? all inputs and outputs are directly ttl-compatible ? common i/o using three-state output ? output enable and two chip enable inputs for easy application ? data retention voltage: 2v (min.) ? available in 32-pin dip, sop tsop and tssop (8 x 13.4mm) packages ? pb-free package only ? all pb-free (lead-free) pr oducts are rohs compliant the lp621024d-t is a low oper ating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5v power supply. inputs and three-stat e outputs are ttl compatible and allow for direct interfacing with common system bus structures. two chip enable inputs are provided for power-down and device enable and an output enable input is included for easy interfacing. data retention is guaranteed at a power supply voltage as low as 2v. product family power dissipation product family operating temperature vcc range speed data retention (i ccdr , typ.) standby (i sb1 , typ.) operating (i cc2 , typ.) package type lp621024d -25 c to +85 c 4.5v~5.5v 55ns / 70ns 0.5 a 2 a 10ma 32l dip/ sop/tsop/ tssop 1. typical values are measured at vcc = 5.0v, t a = 25 c and not 100% tested. 2. data retention current vcc = 2.0v. pin configurations ? dip ? sop ? tsop/(tssop) nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 1 i/o 2 i/o 3 i/o 4 gnd i/o 5 i/o 6 i/o 7 i/o 8 a10 a9 a8 a13 ce2 a15 vcc a11 lp621024d-t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 oe nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 1 i/o 2 i/o 3 i/o 4 gnd i/o 5 i/o 6 i/o 7 i/o 8 a10 a9 a8 a13 ce2 a15 vcc a11 lp621024dm-t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 oe lp621024dv-t (lp621024dx-t) 1 16 17 32 pin no. pin name pin no. pin name 12 a9 3 4 5 6 7 8 9 10 11 12 13 14 30 29 28 27 26 25 24 22 19 21 20 23 18 17 a8 a13 ce2 a15 vcc nc i/o 8 a16 a14 a12 a7 a6 a3 a2 a1 a0 i/o 1 i/o 2 gnd i/o 4 i/o 5 i/o 6 i/o 7 i/o 3 a11 we ce1 15 16 31 32 a5 a4 a10 oe ce1 we ce1 we
lp621024d-t series (july, 2005, version 1.2) 2 amic technology, corp. block diagram row decoder 512 x 2048 memory array input data circuit column i/o control circuit ce2 ce1 we i/o 8 i/o 1 a16 a15 a14 a0 vcc gnd oe pin descriptions - dip/sop pin no. symbol description 1 nc no connection 2 - 12, 23, 25 - 28, 31 a0 - a16 address inputs 13 - 15, 17 - 21 i/o 1 - i/o 8 data input/outputs 16 gnd ground 22 ce1 chip enable 24 oe output enable 29 we write enable 30 ce2 chip enable 32 vcc power supply (+5v) pin description - tsop/tssop pin no. symbol description 1 - 4, 7, 10 - 20, 31 a0 - a16 address inputs 5 we write enable 6 ce2 chip enable 8 vcc power supply 9 nc no connection 21 - 23, 25 - 29 i/o 1 - i/o 8 data input/outputs 24 gnd ground 30 ce1 chip enable 32 oe output enable
lp621024d-t series (july, 2005, version 1.2) 3 amic technology, corp. recommended dc operating conditions (t a = -25 c to + 85 c) symbol parameter min. typ. max. unit supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 3.5 vcc + 0.3 v v il input low voltage -0.3 0 +0.8 v c l output load - - 30 pf ttl output load - - 1 - absolute maximum ratings* vcc to gnd ..............................................-0.5v to + 7.0v in, in/out volt to gnd .................... -0.5v to vcc + 0.5v operating temperature, topr .................. -25 c to + 85 c storage temperatur e, tstg.................... -55 c to + 125 c temperature under bias, tbias............... -10 c to + 85 c power dissipation, p t........................................................................ 0.7w soldering temp . & time ............................. 260 c, 10 sec *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = -25 c to + 85 c, vcc = 5v 10%, gnd = 0v) symbol parameter lp621024d-55llt lp621024d-70llt unit conditions min. max. min. max. ? i li ? input leakage current - 1 - 1 a v in = gnd to vcc ? i lo ? output leakage current - 1 - 1 a ce1 = v ih or ce2 = v il or oe = v ih or we = v il v i/o = gnd to vcc i cc active power supply current - 15 - 15 ma ce1 = v il , ce2 = v ih i i/o = 0ma i cc1 dynamic operating - 70 - 70 ma min. cycle, duty = 100% ce1 = v il , ce2 = v ih i i/o = 0ma i cc2 current - 15 - 15 ma ce1 = v il , ce2 = v ih v ih = vcc, v il = 0v f = 1mh z, i i/o = 0ma
lp621024d-t series (july, 2005, version 1.2) 4 amic technology, corp. dc electrical characteristics (continued) symbol parameter lp621024d-55llt lp621024d-70llt unit conditions min. max. min. max. i sb - 2 - 2 ma ce1 = v ih or ce2 =v il i sb1 standby power supply current - 50 - 50 a ce1 vcc - 0.2v ce2 vcc - 0.2v v in 0v i sb2 - 50 - 50 a ce2 0.2v v in 0v v ol output low voltage - 0.4 - 0.4 v i ol = 2.1ma v oh output high voltage 2.4 - 2.4 - v i oh = -1.0ma truth table mode ce1 ce2 oe we i/o operation supply current standby h x x x high z i sb , i sb1 x l x x high z i sb , i sb2 output disable l h h h high z i cc, i cc1, i cc2 read l h l h d out i cc, i cc1, i cc2 write l h x l d in i cc, i cc1, i cc2 note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 6 pf v in = 0v c i/o * input/output capacitance 8 pf v i/o = 0v * these parameters are sampled and not 100% tested.
lp621024d-t series (july, 2005, version 1.2) 5 amic technology, corp. ac characteristics (t a = -25 c to + 85 c, vcc = 5v 10%) symbol parameter lp621024d-55llt lp621024d-70llt unit min. max. min. max. read cycle t rc read cycle time 55 - 70 - ns t aa address access time - 55 - 70 ns t ace1 chip enable access time ce1 - 55 - 70 ns t ace2 ce2 - 55 - 70 ns t oe output enable to output valid - 30 - 35 ns t clz1 chip enable to output in low z ce1 10 - 10 - ns t clz2 ce2 10 - 10 - ns t olz output enable to output in low z 5 - 5 - ns t chz1 chip disable to output in high z ce1 0 20 0 25 ns t chz2 ce2 0 20 0 25 ns t ohz output disable to output in high z 0 20 0 25 ns t oh output hold from address change 5 - 5 - ns write cycle t wc write cycle time 55 - 70 - ns t cw chip enable to end of write 50 - 60 - ns t as address setup time 0 - 0 - ns t aw address valid to end of write 50 - 60 - ns t wp write pulse width 40 - 50 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z 0 25 0 30 ns t dw data to write time overlap 25 - 30 - ns t dh data hold from write time 0 - 0 - ns t ow output active from end of write 5 - 5 - ns notes: t chz1 , t chz2 , t ohz , and t whz are defined as the time at which the out puts achieve the open circuit condition and are not referred to output voltage levels.
lp621024d-t series (july, 2005, version 1.2) 6 amic technology, corp. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 2 (1, 3, 4, 6) t clz1 5 t ace1 t chz1 5 ce1 d out read cycle 3 (1, 4, 7, 8) t clz2 5 t ace2 t chz2 5 ce2 d out
lp621024d-t series (july, 2005, version 1.2) 7 amic technology, corp. timing waveforms (continued) read cycle 4 (1) t rc address ce2 d out t aa t oe t olz 5 t ace1 t clz1 5 t ace2 t clz2 5 t chz2 5 t ohz 5 t chz1 5 t oh oe ce1 notes: 1. we is high for read cycle. 2. device is continuously enabled ce1 = v il and ce2 = v ih . 3. address valid prior to or coincident with ce1 transition low. 4. oe = v il . 5. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested. 6. ce2 is high. 7. ce1 is low. 8. address valid prior to or coincident with ce2 transition high. write cycle 1 (6) (write enable controlled) t wc address ce1 ce2 d in t ow t dh t dw t whz t wp 2 t as 1 (4) t cw 5 t aw t wr 3 we d out (4)
lp621024d-t series (july, 2005, version 1.2) 8 amic technology, corp. timing waveforms (continued) write cycle 2 (chip enable controlled) t wc address ce1 ce2 d in t dh t dw (4) (4) t cw 5 t aw t wr 3 we d out t whz 7 t wp 2 t cw 5 t as 1 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp ) of a low ce1, a high ce2 and a low we . 3. t wr is measured from the earliest of ce1 or we going high or ce2 going low to the end of the write cycle. 4. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. 6. oe is continuously low. ( oe = v il ) 7. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested.
lp621024d-t series (july, 2005, version 1.2) 9 amic technology, corp. ac test conditions input pulse levels 0v to 3.0v input rise and fall time 5 ns input and output timing reference levels 1.5v output load see figures 1 and 2 +5v i/o 990 ? 1800 ? 30pf* * including scope and jig. +5v i/o 990 ? 1800 ? 5pf* * including scope and jig. figure 1. output load figure 2. output load for t clz1 , t clz2 , t ohz , t olz , t chz1 , t chz2 , t whz , and t ow data retention characteristics (t a = -25 c to 85 c) symbol parameter min. max. unit conditions v dr1 2.0 5.5 v ce1 vcc - 0.2v v dr2 vcc for data retention 2.0 5.5 v ce2 0.2v ce1 vcc - 0.2v or ce1 0.2v i ccdr1 data retention current ll-version - 20** a vcc = 2.0v, ce1 vcc - 0.2v ce2 vcc - 0.2v v in 0v i ccdr2 ll-version - 20** a vcc = 2.0v ce2 0.2v v in 0v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time 5 - ms ** lp621024d-55llt/70llt i ccdr : max. 2 a at t a = 0 c to + 40 c
lp621024d-t series (july, 2005, version 1.2) 10 amic technology, corp. low vcc data retention waveform (1) ( ce1 controlled) vcc ce1 t cdr v ih 4.5v t r v ih 4.5v data retention mode v dr 2v ce1 v dr - 0.2v low vcc data retention waveform (2) (ce2 controlled) vcc ce2 t cdr v il 4.5v t r v il 4.5v data retention mode v dr 2v ce2 < 0.2v
lp621024d-t series (july, 2005, version 1.2) 11 amic technology, corp. ordering information part no. access time (ns) operating current max. (ma) standby current max. ( a) package lp621024d-55lltf 70 50 32l pb-free dip lp621024dm-55lltf 70 50 32l pb-free sop lp621024dv-55lltf 70 50 32l pb-free tsop lp621024dx-55lltf 55 70 50 32l pb-free tssop lp621024d-70lltf 70 50 32l pb-free dip lp621024dm-70lltf 70 50 32l pb-free sop lp621024dv-70lltf 70 50 32l pb-free tsop lp621024dx-70lltf 70 70 50 32l pb-free tssop
lp621024d-t series (july, 2005, version 1.2) 12 amic technology, corp. package information p-dip 32l outline dimensions unit: inches/mm 1 32 e 1 s a 2 a l e e a d c b 1 b a 1 base plane seating plane 16 17 e 1 symbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.1550.010 3.940.25 b 0.018 +0.004 0.46 +0.10 -0.002 -0.05 b 1 0.050 +0.004 1.27 +0.10 -0.002 -0.05 c 0.010 +0.004 0.25 +0.11 -0.002 -0.05 d 1.650 typ. (1.670 max.) 41.91 typ. (42.42 max.) e 0.6000.010 15.240.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.1000.010 2.540.25 l 0.1300.010 3.300.25 0 ~ 15 0 ~ 15 e a 0.6550.035 16.640.89 s 0.090 max. 2.29 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash.
lp621024d-t series (july, 2005, version 1.2) 13 amic technology, corp. package information sop (w.b.) 32l outline dimensions unit: inches/mm 1 e h e l l e c 16 see detail f detail f 17 32 e 1 e 1 a 1 a 2 a s d seating plane d y e b ~ ~ symbol dimensions in inches dimensions in mm a 0.118 max. 3.00 max. a 1 0.004 min. 0.10 min. a 2 0.1060.005 2.690.13 b 0.016 +0.004 0.41 +0.10 -0.002 -0.05 c 0.008 +0.004 0.20 +0.10 -0.002 -0.05 d 0.805 typ. (0.820 max.) 20.45 typ. (20.83 max.) e 0.4450.010 11.300.25 e 0.050 0.006 1.270.15 e 1 0.525 nom. 13.34 nom. h e 0.5560.010 14.120.25 l 0.0310.008 0.790.20 l e 0.0550.008 1.400.20 s 0.044 max. 1.12 max. y 0.004 max. 0.10 max. 0 ~ 10 0 ~ 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
lp621024d-t series (july, 2005, version 1.2) 14 amic technology, corp. package information tsop 32l type i (8 x 20mm) outline dimensions unit: inches/mm e l e l gauge plane a a 2 c 0.25 bsc detail "a" d y detail "a" s a 1 b h d d e 0.10(0.004) m 12.0 symbol dimensions in inches dimensions in mm a 0.047 max. 1.20 max. a 1 0.0040.002 0.100.05 a 2 0.0390.002 1.000.05 b 0.0080.001 0.200.03 c 0.0060.001 0.150.02 d 0.7240.004 18.400.10 e 0.3150.004 8.000.10 e 0.020 typ. 0.50 typ. h d 0.7870.007 20.000.20 l 0.0200.004 0.500.10 l e 0.031 typ. 0.80 typ. s 0.0167 typ. 0.425 typ. y 0.004 max. 0.10 max. 0 ~ 6 0 ~ 6 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
lp621024d-t series (july, 2005, version 1.2) 15 amic technology, corp. package information tssop 32l type i (8 x 13.4mm) outline dimensions unit: inches/mm e detail "a" d 0.10mm detail "a" s b d 1 e d l e l gauge plane a a 2 c 0.25 bsc detail "a" a 1 seating plane 12.0 symbol dimensions in inches dimensions in mm a 0.049 max. 1.25 max. a 1 0.002 min. 0.05 min. a 2 0.0390.002 1.000.05 b 0.0080.001 0.200.03 c 0.0060.0003 0.150.008 e 0.3150.004 8.000.10 e 0.020 typ. 0.50 typ. d 0.5280.008 13.400.20 d 1 0.4650.004 11.800.10 l 0.020.008 0.500.20 l e 0.0266 min. 0.675 min. s 0.0109 typ. 0.278 typ. y 0.004 max. 0.10 max. 0 ~ 6 0 ~ 6 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.

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